1. Field of the Invention
The present invention relates to a decoder circuit, and more particularly to a decoder circuit for driving word lines of a semiconductor memory device.
2. Description of the Related Art
Conventionally, a semiconductor memory device is provided with a decoder circuit (row decoder) for driving word lines. As disclosed in Japanese Laid-Open Patent Publication No. 8-236718, a decoder circuit (row decoder) includes a first decoder (decoder circuit) and a second decoder (word line driver). The first decoder operates according to a first address signal, and the second decoder operates according to an output of the first decoder and a second address signal. The second decoder has a PMOS transistor and an NMOS transistor connected in series between a node for receiving the output of the first decoder and a ground node for receiving a ground voltage. The gates of the PMOS transistor and the NMOS transistor receive the second address signal different from the first address signal input into the first decoder. The voltage generated at a connection node between these transistors is outputted as a word line drive voltage.
Conventionally, to drive the decoder circuit, not only the output of the second decoder but also the output of the first decoder oscillate between the power supply potential Vdd and the ground potential VSS. In this relation, to increase the drive speed of the decoder circuit and reduce the charge amount consumed by the decoder circuit, the peak to peak amplitude of the output of the first decoder should desirably be smaller than the peak to peak amplitude from the power supply potential Vdd to the ground potential VSS.